View ISPLSI1048EA-100LQ128_26709.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ispLSI 1048EA
(R)
In-System Programmable High Density PLD Features
* HIGH DENSITY PROGRAMMABLE LOGIC -- 8,000 PLD Gates -- 96 I/O Pins, Eight Dedicated Inputs -- 288 Registers -- High-Speed Global Interconnects -- Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. -- Small Logic Block Size for Random Logic -- Functionally Compatible with ispLSI 1048C and 1048E * NEW FEATURES -- 100% IEEE 1149.1 Boundary Scan Testable -- ispJTAGTM In-System Programmable Via IEEE 1149.1 (JTAG) Test Access Port -- User Selectable 3.3V or 5V I/O supports Mixed Voltage Systems (VCCIO Pin) -- Open Drain Output Option TECHNOLOGY * HIGH PERFORMANCE -- fmax = 170 MHz Maximum Operating Frequency -- tpd = 5.0 ns Propagation Delay -- TTL Compatible Inputs and Outputs -- Electrically Eraseable and Reprogrammable -- Non-Volatile -- 100% Tested at Time of Manufacture * IN-SYSTEM PROGRAMMABLE -- Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality -- Reprogram Soldered Devices for Faster Prototyping * OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS -- Complete Programmable Device Can Combine Glue Logic and Structured Designs -- Enhanced Pin Locking Capability -- Four Dedicated Clock Input Pins -- Synchronous and Asynchronous Clocks -- Programmable Output Slew Rate Control to Minimize Switching Noise -- Flexible Pin Placement -- Optimized Global Routing Pool Provides Global Interconnectivity * ispDesignEXPERTTM - LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING -- Superior Quality of Results -- Tightly Integrated with Leading CAE Vendor Tools -- Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZERTM -- PC and UNIX Platforms E2CMOS(R)
Functional Block Diagram
Output Routing Pool F7 F6 F5 F4 F3 F2 F1 F0 A0
Output Routing Pool
Output Routing Pool E7 E6 E5 E4 E3 E2 E1 E0 D7 D5
Output Routing Pool
DQ
A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 Output Routing Pool
D6
Logic
DQ
Global Routing Pool (GRP)
Array
DQ
GLB
D4 D3 D2 D1 D0
DQ
C0 C1 C2 C3 C4 C5 C6 C7 Output Routing Pool
CLK
0139A/1048EA
Description
The ispLSI 1048EA is a High Density Programmable Logic Device containing 288 Registers, 96 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins, two dedicated Global OE input pins, and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1048EA features 5V in-system programmability and in-system diagnostic capabilities via IEEE 1149.1 Test Access Port. The ispLSI 1048EA offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. A functional superset of the ispLSI 1048 architecture, the ispLSI 1048EA device adds user selectable 3.3V or 5V I/O and open-drain output options. The basic unit of logic on the ispLSI 1048EA device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1...F7 (see Figure 1). There are a total of 48 GLBs in the ispLSI 1048EA device. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device.
Copyright (c) 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
June 2000
1048ea_03
1
Specifications ispLSI 1048EA
Functional Block Diagram
Figure 1. ispLSI 1048EA Functional Block Diagram
I/O I/O I/O I/O 95 94 93 92 RESET
GOE 0 GOE 1
I/O I/O I/O I/O 91 90 89 88
I/O I/O I/O I/O 87 86 85 84
I/O I/O I/O I/O 83 82 81 80
IN IN 11 10
I/O I/O I/O I/O 79 78 77 76
I/O I/O I/O I/O 75 74 73 72
I/O I/O I/O I/O 71 70 69 68
I/O I/O I/O I/O 67 66 65 64
IN 9
IN 8
Input Bus Generic Logic Blocks (GLBs) F7 F6 Output Routing Pool (ORP) F5 F4 F3 F2 F1 F0 E7 E6
Input Bus Output Routing Pool (ORP) E5 E4 E3 E2 E1 E0
IN 7 IN 6 I/O 63 I/O 62 I/O 61 I/O 60
VCCIO
D7
I/O 0 I/O 1 I/O 2 I/O 3
A0 A1
D6
Output Routing Pool (ORP)
D5
I/O 59 I/O 58 I/O 57
Output Routing Pool (ORP)
D4 D3 D2 D1 D0
lnput Bus
Input Bus
I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7
Global Routing Pool (GRP)
I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 I/O 49 I/O 48
C0
C1
C2
C3
C4
C5
C6
C7
Clock Distribution Network
Megablock
TDI TDO TMS TCK IN 2 I/O I/O I/O I/O 16 17 18 19 I/O I/O I/O I/O 20 21 22 23 I/O I/O I/O I/O 24 25 26 27 I/O I/O I/O I/O 28 29 30 31 IN 4 I/O I/O I/O I/O 32 33 34 35 I/O I/O I/O I/O 36 37 38 39 I/O I/O I/O I/O 40 41 42 43 I/O I/O I/O I/O 44 45 46 47
Output Routing Pool (ORP) Input Bus
Output Routing Pool (ORP) Input Bus
CLK 0 CLK 1 CLK 2 IOCLK 0 IOCLK 1
YYYY 0123
0139F/1048EA
The device also has 96 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, registered input, latched input, output or bi-directional I/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source 2mA or sink 8mA. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise. By connecting the VCCIO pin to a common 5V or 3.3V power supply, I/O output levels can be matched to 5V or 3.3V compatible voltages. Eight GLBs, 16 I/O cells, dedicated inputs (if available) and one ORP are connected together to make a Megablock (Figure 1). The outputs of the eight GLBs are connected to a set of 16 universal I/O cells by the ORP. Each ispLSI 1048EA device contains six Megablocks. The GRP has, as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew.
Clocks in the ispLSI 1048EA device are selected using the Clock Distribution Network. Four dedicated clock pins (Y0, Y1, Y2 and Y3) are brought into the distribution network, and five clock outputs (CLK 0, CLK 1, CLK 2, IOCLK 0 and IOCLK 1) are provided to route clocks to the GLBs and I/O cells. The Clock Distribution Network can also be driven from a special clock GLB (D0). The logic of this GLB allows the user to create an internal clock from a combination of internal signals within the device.
Programmable Open-Drain Outputs
In addition to the standard output configuration, the outputs of the ispLSI 1048EA are individually programmable, either as a standard totem-pole output or an open-drain output. The totem-pole output drives the specified Voh and Vol levels, whereas the open-drain output drives only the specified Vol. The Voh level on the open-drain output depends on the external loading and pull-up. This output configuration is controlled by a programmable fuse. The default configuration when the device is in bulk erased state is totem-pole configuration. The open-drain/totem-pole option is selectable through the ispDesignEXPERT software tools.
2
Specifications ispLSI 1048EA
Boundary Scan
Figure 2. Boundary Scan Waveforms and Timing Specifications
TMS
TDI Tbtsu Tbtch TCK Tbtcl Tbth Tbtcp
Tbtvo TDO Valid Data
Tbtco Valid Data
Tbtoz
Tbtcpsu Data to be captured
Tbtcph Data Captured
Tbtuov Data to be driven out
Tbtuco Valid Data
Tbtuoz Valid Data
Symbol tbtcp tbtch
tbtcl tbtsu tbth trf tbtco tbtoz tbtvo tbtcpsu tbtcph tbtuco tbtuoz tbtuov
Parameter TCK [BSCAN test] clock pulse width TCK [BSCAN test] pulse width high TCK [BSCAN test] pulse width low TCK [BSCAN test] setup time TCK [BSCAN test] hold time TCK [BSCAN test] rise and fall time TAP controller falling edge of clock to valid output TAP controller falling edge of clock to data output disable TAP controller falling edge of clock to data output enable BSCAN test Capture register setup time BSCAN test Capture register hold time BSCAN test Update reg, falling edge of clock to valid output BSCAN test Update reg, falling edge of clock to output disable BSCAN test Update reg, falling edge of clock to output enable
Min 100 50 50 20 25 50 - - - 40 25 - - -
Max - - - - - - 25 25 25 - - 50 50 50
Units ns ns ns ns ns mV/ns ns ns ns ns ns ns ns ns
3
Specifications ispLSI 1048EA
Absolute Maximum Ratings 1
Supply Voltage Vcc. ................................. -0.5 to +7.0V Input Voltage Applied ........................ -2.5 to VCC +1.0V Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V Storage Temperature ................................ -65 to 150C Case Temp. with Power Applied .............. -55 to 125C Max. Junction Temp. (TJ) with Power Applied ... 150C
1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).
DC Recommended Operating Conditions
SYMBOL PARAMETER Supply Voltage Supply Voltage: Output Drivers Input Low Voltage Input High Voltage Commercial 5V 3.3V TA = 0C to + 70C MIN. 4.75 4.75 3.0 0 2.0 MAX. 5.25 5.25 3.6 0.8 Vcc+1 UNITS V V V V V
VCC VCCIO VIL VIH
Table 2-0005/1048EA
Capacitance (TA=25oC, f=1.0 MHz)
SYMBOL PARAMETER Dedicated Input, I/O, Y1, Y2, Y3, Clock Capacitance Y0 Clock Capacitance TYPICAL 8 10 UNITS pf pf TEST CONDITIONS VCC = 5.0V, VPIN = 2.0V VCC = 5.0V, VPIN = 2.0V
Table 2-0006/1048EA
C1 C2
Erase/Reprogram Specifications
PARAMETER Erase/Reprogram Cycles MINIMUM 10000 MAXIMUM - UNITS Cycles
Table 2-0008/1048EA
4
Specifications ispLSI 1048EA
Switching Test Conditions
Input Pulse Levels Input Rise and Fall Time 10% to 90% Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. GND to 3.0V 1.5ns 1.5V 1.5V See Figure 3
Table 2-0003/1048EA
Figure 3. Test Load
+ 5V R1 Device Output R2 CL* Test Point
Output Load Conditions (see Figure 3)
TEST CONDITION A B Active High Active Low Active High to Z at VOH -0.5V Active Low to Z at VOL +0.5V R1 470 470 470 R2 390 390 390 390 390 CL 35pF 35pF 35pF 5pF 5pF
Table 2-0004a
*CL includes Test Fixture and Probe Capacitance.
0213a
C
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL PARAMETER Output Low Voltage Output High Voltage Input or I/O Low Leakage Current Input or I/O High Leakage Current I/O Active Pull-Up Current Output Short Circuit Current Operating Power Supply Current IOL = 8 mA IOH = -2 mA, VCCIO = 3.0V IOH = -4 mA, VCCIO = 4.75V 0V VIN VIL (Max.) (VCCIO - 0.2)V VIN VCCIO VCCIO VIN 5.25V 0V VIN VIL VCCIO = 5.0V or 3.3V, VOUT = 0.5V VIL = 0.0V, VIH = 3.0V fTOGGLE = 1 MHz CONDITION MIN. -- 2.4 2.4 -- -- -- -- -- -- TYP.3 -- -- -- -- -- -- -- -- 190 MAX. UNITS 0.4 -- -- -10 10 10 -200 -240 -- V V V A A A A mA mA
VOL VOH IIL IIH IIL-PU IOS1 ICC2, 4, 5
Table 2-0007/1048EA 1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 2. Meaured using eight 16-bit counters. 3. Typical values are at VCC = 5V and TA = 25C. 4. Unused inputs held at 0.0V. 5. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption section of this data sheet and the Thermal Management section of the Lattice Semiconductor Data Book CD-ROM to estimate maximum ICC.
5
Specifications ispLSI 1048EA
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER TEST COND.
4
#
2
DESCRIPTION
1
-170 -- -- 170
1
-125 -- -- 125 100 167 4.5 -- 0.0 5.5 -- 0.0 -- 5.0 -- -- -- -- 3.0 3.0 3.0 0.0 7.5 10.0 -- -- -- -- 4.5 -- -- 5.5 -- 10.0 -- 12.0 12.0 7.0 7.0 -- -- -- --
-100 -- -- 100 77 125 6.0 -- 0.0 7.0 -- 0.0 -- 6.5 -- -- -- -- 4.0 4.0 3.5 0.0 10.0 12.5 -- -- -- -- 6.0 -- -- 7.0 -- 13.5 -- 15.0 15.0 9.0 9.0 -- -- -- --
MIN. MAX. MIN. MAX. MIN. MAX. 5.0 7.0 -- -- -- -- 3.5 -- -- 4.5 -- 7.0 -- 9.0 9.0 6.5 6.5 -- -- -- --
UNITS ns ns MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tpd1 tpd2 fmax (Int.) fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 tptoeen tptoedis tgoeen tgoedis twh twl tsu3 th3
1. 2. 3. 4.
A A A -- -- -- A -- -- -- -- A -- B C B C -- -- -- --
1 2 3 4 5 6 7 8 9
Data Propagation Delay, 4PT Bypass, ORP Bypass Data Propagation Delay, Worst Case Path Clock Frequency with Internal Feedback 3 Clock Frequency, Max. Toggle
Clock Frequency with External Feedback ( tsu2 + tco1) 125
(
1 twh + twl
)
222 3.5 -- 0.0 4.5 -- 0.0 -- 4.0 -- -- -- -- 2.25 2.25
GLB Reg. Setup Time before Clock,4 PT Bypass GLB Reg. Clock to Output Delay, ORP Bypass GLB Reg. Hold Time after Clock, 4 PT Bypass GLB Reg. Setup Time before Clock
10 GLB Reg. Clock to Output Delay 11 GLB Reg. Hold Time after Clock 12 Ext. Reset Pin to Output Delay 13 Ext. Reset Pulse Duration 14 Input to Output Enable 15 Input to Output Disable 16 Global OE Output Enable 17 Global OE Output Disable 18 External Synchronous Clock Pulse Duration, High 19 External Synchronous Clock Pulse Duration, Low 20 21
I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3) 3.0 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3) 0.0
Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock. Refer to Timing Model in this data sheet for further details. Standard 16-bit counter using GRP feedback. Reference Switching Test Conditions section.
Table 2-0030A/1048EA v.2.0
6
Specifications ispLSI 1048EA
Internal Timing Parameters1
PARAMETER Inputs #2 -170 DESCRIPTION -125 -100 MIN. MAX. MIN. MAX. MIN. MAX. -- -- 3.0 0.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.3 2.0 -- -- -- -- 1.7 -- -- -- 0.3 4.0 -- -- 4.6 4.6 1.8 1.4 1.6 1.8 2.2 3.8 2.1 2.0 2.3 2.2 2.2 1.0 -- -- 1.4 4.7 2.7 3.6 2.7 0.1 1.0 0.1 -- -- 3.0 0.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.3 3.5 -- -- -- -- 2.8 -- -- -- 0.3 4.0 -- -- 4.6 4.6 1.9 1.7 1.9 2.1 2.5 4.1 3.4 3.1 3.6 3.6 3.6 1.2 -- -- 1.4 4.9 3.8 5.2 3.9 0.6 1.3 0.2 -- -- 3.4 0.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.3 4.8 -- -- -- -- 3.5 -- -- -- 0.4 4.0 -- -- 5.0 5.0 2.2 2.1 2.3 2.5 2.9 4.5 4.9 4.9 4.3 4.3 4.3 2.1 -- -- 1.7 5.0 4.5 7.2 4.7 1.4 1.4 0.4 UNITS
tiobp tiolat tiosu tioh tioco tior tdin
GRP
22 I/O Register Bypass 23 I/O Latch Delay 24 I/O Register Setup Time before Clock 25 I/O Register Hold Time after Clock 26 I/O Register Clock to Out Delay 27 I/O Register Reset to Out Delay 28 Dedicated Input Delay 29 GRP Delay, 1 GLB Load 30 GRP Delay, 4 GLB Loads 31 GRP Delay, 8 GLB Loads 32 GRP Delay, 16 GLB Loads 33 GRP Delay, 48 GLB Loads 34 4 Product Term Bypass Path Delay (Combinatorial) 35 4 Product Term Bypass Path Delay (Registered) 36 1 Product Term/XOR Path Delay 37 20 Product Term/XOR Path Delay 38 XOR Adjacent Path Delay 3 39 GLB Register Bypass Delay 40 GLB Register Setup Time before Clock 41 GLB Register Hold Time after Clock 42 GLB Register Clock to Output Delay 43 GLB Register Reset to Output Delay 44 GLB Product Term Reset to Register Delay 45 GLB Product Term Output Enable to I/O Cell Delay 46 GLB Product Term Clock Delay 47 GLB Feedback Delay 48 ORP Delay 49 ORP Bypass Delay
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tgrp1 tgrp4 tgrp8 tgrp16 tgrp48
GLB
t4ptbpc t4ptbpr t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgro tptre tptoe tptck tgfb
ORP
torp torpbp
1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros.
Table 2-0036A/1048EA v.2.0
7
Specifications ispLSI 1048EA
Internal Timing Parameters1
PARAMETER Outputs # DESCRIPTION -170 -125 -100 MIN. MAX. MIN. MAX. MIN. MAX. -- -- -- -- -- 0.9 0.9 0.8 0.0 0.8 -- 0.9 6.0 3.3 3.3 2.6 0.9 0.9 1.8 0.0 2.8 0.4 -- -- -- -- -- 1.1 0.9 0.8 0.0 0.8 -- 1.7 6.0 4.0 4.0 3.0 1.1 0.9 1.8 0.0 2.8 2.1 -- -- -- -- -- 1.9 1.5 0.8 0.0 0.8 -- 2.0 6.0 5.1 5.1 3.9 1.9 1.5 1.8 0.0 2.8 5.1 UNITS
tob tsl toen todis tgoe
Clocks
50 Output Buffer Delay 51 Output Slew Limited Delay Adder 52 I/O Cell OE to Output Enabled 53 I/O Cell OE to Output Disabled 54 Global OE 55 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 56 Clock Delay, Y1 or Y2 to Global GLB Clock Line 57 Clock Delay, Clock GLB to Global GLB Clock Line 58 Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line 59 Clock Delay, Clock GLB to I/O Cell Global Clock Line 60 Global Reset to GLB and I/O Registers
ns ns ns ns ns ns ns ns ns ns ns
tgy0 tgy1/2 tgcp tioy2/3 tiocp
Global Reset
tgr
1. Internal timing parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details.
Table 2-0037A/1048EA v.2.0
8
Specifications ispLSI 1048EA
ispLSI 1048EA Timing Model
I/O Cell GRP #47 Ded. In GLB Feedback #34 GRP4 #30 GRP Loading Delay #29, 31 - 33 Comb 4 PT Bypass GLB Reg Bypass #39 GLB Reg Delay D RST Reset #60 #40 - 43 Q ORP Bypass #49 ORP Delay #48 #50, 51 I/O Pin (Output) ORP I/O Cell
#28 I/O Reg Bypass #22 Input D Register Q RST #23 - 27
I/O Pin (Input)
Reg 4 PT Bypass #35 20 PT XOR Delays #36 - 38
#52, 53
#60
Clock Distribution Y1,2,3 #56 - 59
Control RE PTs OE #44 - 46 CK
0491/1048EA
Y0 GOE 0,1
#55 #54
Derivations of tsu, th and tco from the Product Term Clock 1 tsu
= = = 0.8 = = = = 2.5 = = = = 7.9 = Logic + Reg su - Clock (min) (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tiobp + tgrp4 + tptck(min)) (#22 + #30 + #37) + (#40) - (#22 + #30 + #46) (0.3 + 1.6 + 2.2) + (0.3) - (0.3 + 1.6 + 1.7) Clock (max) + Reg h - Logic (tiobp + tgrp4 + tptck(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor) (#22 + #30 + #46) + (#41) - (#22 + #30 + #37) (0.3 + 1.6 + 2.7) + (2.0) - (0.3 + 1.6 + 2.2) Clock (max) + Reg co + Output (tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob) (#22 + #30 + #46) + (#42) + (#48 + #50) (0.3 + 1.6 + 2.7) + (1.4) + (1.0 + 0.9)
th
tco
Derivations of tsu, th and tco from the Clock GLB 1 tsu
= = = 1.3 = = = = 2.0 = = = = 7.4 = Logic + Reg (setup) - Clock (min) (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tgy0(min) + tgco + tgcp(min)) (#22 + #30 + #37) + (#40) - (#55 + #42 + #57) (0.3 + 1.6 + 2.2) + (0.3) - (0.9 + 1.4 + 0.8) Clock (max) + Reg (hold) - Logic (tgy0(max) + tgco + tgcp(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor) (#55 + #42 + #57) + (#41) - (#22 + #30 + #37) (0.9 + 1.4 + 1.8) + (2.0) - (0.3 + 1.6 + 2.2) Clock (max) + Reg(clock-to-out) + Output (tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob) (#55 + #42 + #57) + (#42) + (#48 + #50) (0.9 + 1.4 + 1.8) + (1.4) + (1.0 + 0.9)
th
tco
1. Calculations are based upon timing specifications for the ispLSI 1048EA-170.
Table 2-0042/1048EA v.2.0
9
Specifications ispLSI 1048EA
Maximum GRP Delay vs. GLB Loads
5
ispLSI 1048EA-100
GRP Delay (ns)
4
ispLSI 1048EA-125 ispLSI 1048EA-170
3
2
1
148
16 32 48 GRP/GLB/1048EA GLB Load
Power Consumption
Power consumption in the ispLSI 1048EA device depends on two primary factors: the speed at which the device is operating and the number of Product Terms Figure 4. Typical Device Power Consumption vs fmax
500 400
ICC (mA)
ispLSI 1048EA
used. Figure 4 shows the relationship between power and operating speed.
300 200 100 0 25 50 75 100 125 fmax (MHz)
150
175
Notes: Configuration of twelve 16-bit counters, Typical current at 5V, 25C
Icc can be estimated for the ispLSI 1048EA using the following equation: Icc = 20mA + (# of PTs * .45) + (# of nets * Max Freq * .0087) Where: # of PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max freq = Highest Clock Frequency to the device (in MHz) The Icc estimate is based on typical conditions (Vcc = 5.0V, room temperature) and an assumption of four GLB loads on average exists. These values are for estimates only. Since the value of Icc is sensitive to operating conditions and the program in the device, the actual Icc should be verified. 0127/1048EA
Package Thermal Characteristics
For the ispLSI 1048EA-170, it is strongly recommended that the actual Icc be verified to ensure that the maximum junction temperature (TJ) with power supplied is not exceeded. Depending on the specific logic design and clock speed, airflow may be required to satisfy the maxi10 mum allowable junction temperature (TJ) specification. Please refer to the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM for additional information on calculating TJ.
Specifications ispLSI 1048EA
Pin Description
NAME
I/O 0 - I/O 5 I/O 6 - I/O 11 I/O 12 - I/O 17 I/O 18 - I/O 23 I/O 24 - I/O 29 I/O 30 - I/O 35 I/O 36 - I/O 41 I/O 42 - I/O 47 I/O 48 - I/O 53 I/O 54 - I/O 59 I/O 60 - I/O 65 I/O 66 - I/O 71 I/O 72 - I/O 77 I/O 78 - I/O 83 I/O 84 - I/O 89 I/O 90 - I/O 95 GOE0, GOE1
PQFP / TQFP PIN NUMBERS
21, 27, 34, 40, 52, 58, 66, 72, 85, 91, 98, 104, 117, 123, 2, 8, 64, 22, 28, 35, 41, 53, 59, 67, 73, 86, 92, 99, 105, 118, 124, 3, 9, 114 51 14 84, 110, 111, 115, 23, 29, 36, 42, 54, 60, 68, 74, 87, 93, 100, 106, 119, 125, 4, 10, 24, 30, 37, 43, 55, 61, 69, 75, 88, 94, 101, 107, 120, 126, 5, 11, 25, 31, 38, 44, 56, 62, 70, 76, 89, 95, 102, 108, 121, 127, 6, 12, 26, 32, 39, 45, 57, 63, 71, 77, 90, 96, 103, 109, 122, 128, 7, 13
DESCRIPTION
Input/Output Pins - These are the general purpose I/O pins used by the logic array.
Global Output Enable input pins. Dedicated input pins to the device.
IN 2, IN 4, IN 6-IN 11 47, 116, TDI 20
Input - Functions as an input pin to load programming data into the device and also is used as one of the two control pins for the ISP JTAG state machine. Input - Controls the operation of the ISP JTAG state machine. Output - Functions as an output pin to read serial shift register data. Input - Functions as a clock pin for the Serial Shift Register. Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device. Dedicated Clock input. This clock input is connected to one of the clock inputs of all of the GLBs on the device. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB on the device. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB and/or any I/O cell on the device. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any I/O cell on the device. 17, 112 48, 33, 82, 49, 113 65, 81, Ground (GND) VCC Supply voltage for output drivers, 5V or 3.3V.
Table 2-0002C/1048EA
TMS TDO TCK RESET Y0 Y1
46 50 78 19 15 83
Y2
80
Y3
79
GND VCC VCCIO
1, 97, 16, 18
11
Specifications ispLSI 1048EA
Pin Configuration
ispLSI 1048EA 128-Pin PQFP Pinout Diagram
I/O 83 I/O 82 I/O 81 I/O 80 I/O 79 I/O 78 I/O 77 I/O 76 I/O 75 I/O 74 I/O 73 I/O 72 IN 10 IN 9 GOE 1 VCC GND IN 8 IN 7 I/O 71 I/O 70 I/O 69 I/O 68 I/O 67 I/O 66 I/O 65 I/O 64 I/O 63 I/O 62 I/O 61 I/O 60 GND 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97
GND I/O 84 I/O 85 I/O 86 I/O 87 I/O 88 I/O 89 I/O 90 I/O 91 I/O 92 I/O 93 I/O 94 I/O 95 IN 11 Y0 VCC GND VCCIO RESET TDI I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
ispLSI 1048EA
Top View
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
I/O 59 I/O 58 I/O 57 I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 I/O 49 I/O 48 IN 6 Y1 VCC GND Y2 Y3 TCK I/O 47 I/O 46 I/O 45 I/O 44 I/O 43 I/O 42 I/O 41 I/O 40 I/O 39 I/O 38 I/O 37 I/O 36 GND
GND I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 TMS IN 2 VCC GND TDO IN 4 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 I/O 32 I/O 33 I/O 34 I/O 35 GOE 0
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
0124/1048EA
12
Specifications ispLSI 1048EA
Pin Configuration
ispLSI 1048EA 128-Pin TQFP Pinout Diagram
I/O 83 I/O 82 I/O 81 I/O 80 I/O 79 I/O 78 I/O 77 I/O 76 I/O 75 I/O 74 I/O 73 I/O 72 IN 10 IN 9 GOE 1 VCC GND IN 8 IN 7 I/O 71 I/O 70 I/O 69 I/O 68 I/O 67 I/O 66 I/O 65 I/O 64 I/O 63 I/O 62 I/O 61 I/O 60 GND 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97
GND I/O 84 I/O 85 I/O 86 I/O 87 I/O 88 I/O 89 I/O 90 I/O 91 I/O 92 I/O 93 I/O 94 I/O 95 IN 11 Y0 VCC GND VCCIO RESET TDI I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
ispLSI 1048EA
Top View
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
I/O 59 I/O 58 I/O 57 I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 I/O 49 I/O 48 IN 6 Y1 VCC GND Y2 Y3 TCK I/O 47 I/O 46 I/O 45 I/O 44 I/O 43 I/O 42 I/O 41 I/O 40 I/O 39 I/O 38 I/O 37 I/O 36 GND
GND I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 TMS IN 2 VCC GND TDO IN 4 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 I/O 32 I/O 33 I/O 34 I/O 35 GOE 0
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
128TQFP/1048EA
13
Specifications ispLSI 1048EA
Part Number Description
ispLSI 1048EA - XXX
Device Family Device Number Speed 170 = 170 MHz fmax 125 = 125 MHz fmax 100 = 100 MHz fmax
X
XXXX
X
Grade Blank = Commercial Package Q128 = 128-Pin PQFP T128 = 128-Pin TQFP Power L = Low
0212/1048EA
ispLSI 1048EA Ordering Information
COMMERCIAL
FAMILY fmax (MHz) 170* 170* ispLSI 125 125 100 100 tpd (ns) 5.0 5.0 7.5 7.5 10 10 ORDERING NUMBER ispLSI 1048EA-170LQ128 ispLSI 1048EA-170LT128 ispLSI 1048EA-125LQ128 ispLSI 1048EA-125LT128 ispLSI 1048EA-100LQ128 ispLSI 1048EA-100LT128 PACKAGE 128-Pin PQFP 128-Pin TQFP 128-Pin PQFP 128-Pin TQFP 128-Pin PQFP 128-Pin TQFP
Table 2-0041A/1048EA
*Note: Please refer to the Package Thermal Characteristics section of this data sheet for details.
14

▲Up To Search▲

Price & Availability of ISPLSI1048EA-100LQ128

	To Download ISPLSI1048EA-100LQ128 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .